发明名称 Ghost reduction circuit arrangement for a television receiver.
摘要 <p>The output signals from the first set of delay elements (111' to 114') of n each with a first delay time (τ') are selectively applied to a second set of delay elements (211 to 214) of m each with a second delay time (T") by means of switch (403). The output signals from the said first and said second of delay elements are processed by the indivisual gain controllable circuits (102', 201) and are composed by an adder (105', 204). The gains (a,, a2, ... an; bo, n1, ... bn) of the gain controllable circuits (102', 201) are respectively controlled by output signals from the control voltage generating circuits (102', 201) which are set by the output signals from comparators (104', 203) for comparing the television signal supplied to the input terminal (100') with a reference signal from the reference signal generating circuit (103'), so that the ghost interference in the television receiver can be reduced by a lesser number of delay elements by subtracting the output signals of the adder circuits (105', 203) from the television input signal in subtractor circuits (106', 205).</p>
申请公布号 EP0055566(A2) 申请公布日期 1982.07.07
申请号 EP19810305968 申请日期 1981.12.18
申请人 HITACHI, LTD. 发明人 KUROYANAGI, TOMOMITSU
分类号 H04N5/21;(IPC1-7):04N5/21 主分类号 H04N5/21
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