| 摘要 |
PURPOSE:To enable the correction of a plurality of errors in the same word and to increase the reliability of memory, by corresponding the address at error generation in a memory block to another word location. CONSTITUTION:If a data read out from memories M1, M2 has one bit error, a plurality of errors are generated in the same word and an error detection signal is generated. This signal is corresponded to either one of timing circuits 3, 4 as an inversion signal. For example, at the circuit 3, the inversion signal via an NOT circuit 6 outputs a negative logic of a basic timing signal as a timing signal to an address multiplexer 1. Thus, the circuit 1 gives a row address in the timing to be applied to a column address M1 in the row address in the input address and applies the column address in the timing to apply the row address. Thus, correction can be made with one bit error correction and two-bit error detection mechanism. |
