| 摘要 |
PURPOSE:To minimize the effect due to out of synchronization by inserting the frame start code of a prescribed bit pattern to which one bit takes at least one logic state to a frame outputted from a parallel/serial conversion means so as to send a signal through other channel even if a transmission error takes place other than the frame start pattern. CONSTITUTION:A FIFO 24 receives a bit serial data from a 15-channel line 20. The data fetching timing of the FIFO 24 is regulated by an enable signal 32 from a control circuit 30 driven by a clock 46 generated by a local oscillation circuit 28. The parallel/serial conversion circuit 26 receives an output 32 from the FIFO 24 to generate a frame shown in figure and outputs it to an output 22 in bit serial. Plural bits (in this example, 5-bit of '01111') representing the frame start pattern 10 are inputted fixedly to the leading in the serial advancing direction of the parallel conversion circuit 26. That is, at least one bit in the plural bits takes one logic state and the prescribed logic takes the logic interrupting the continuity of the bit logic state before and after the bit insertion. |
