| 摘要 |
PURPOSE:To produce CMOS devices of N channel FET featuring higher withstand voltage by a construction wherein two or more different types of regions are produced to have different concentrations on a channel stopper region formed on a P well region, and the source and drain are formed in contact with the low concentration region. CONSTITUTION:Resist coatings 5 with an opening for a region A on which a channel stopper is to be produced in high concentration is applied after the P well 4 is provided on an N-type substrate 1 to form a nitride film 3 on region for formation of an FET in order to form a boron ion implantation layer B. Next, boron ion implantation layer C is formed through the opening of a resist coatings 6 covering ends of the nitride films 3 on the P well region. Next, after forming phosphorous ion implantation layers F are formed through resist coatings 8 on the P channel region, selective oxidizing treatment is made to produce a structure having the channel stopper region consisting of a low concentration region 11 and a high concentration region 10 under separate oxide layers 9 in the P well. Consecutively, an FET having an offset drain, for example, is formed to produce a CMOS device. By such a procedure, a small, high speed circuit of higher junction withstand voltage can be produced. |
