发明名称 FFT ADDRESS GENERATOR
摘要 PURPOSE:To obtain an FET address synchronizing with clock pulses, by permitting a spertral analyzer, which performs spectrum analysis by digital signal processing, to use changeover switches and a decoder by synchronizing with the clock pulses. CONSTITUTION:When the least significant digit bit LSB (3a) is connected to an output lien 8h, an offset signal 5 controls changeover switches 12b-12h simultaneously and relationally. Then, changeover switches which correspond to higher digit bits than an output signal to which the LSB (3a) is connected are connected to upper contacts, and changeover switches which correspond to lower digit bits than the output line are connected to lower contacts respectively. Thus, the swithces 12b-12h and a decoder 11 are used in combination to output an FET address 8 synchronizing with clock pulses 1.
申请公布号 JPS57106981(A) 申请公布日期 1982.07.03
申请号 JP19800183114 申请日期 1980.12.23
申请人 MITSUBISHI DENKI KK 发明人 ITOU MASAYA
分类号 G01R23/16;G06F17/14 主分类号 G01R23/16
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