| 摘要 |
PURPOSE:To enhance practically the speed of the synchronizing processing in the receiving side to accelerate the communication speed, by dividing a synchronizing signal into an optional number of phases and by transmitting them. CONSTITUTION:A synchronizing signal is divided into four phases and the synchronizing pattern of each phase includes signals of each phase in every 4 bits. in the receiving side, the number of phase shift bits of each synchronizing pattern is detected to discriminate the phase, and a frame synchronizing point is determined. At this time, the speed of the receiving synchronizing pattern is the 1/4 of the transmission speed. In this case, a CPU1 fetches every 8 or 7 bits of data which are sampled from receiving data RD at every 4 bits and are stored in a shift register 3 and discriminates the synchronizing signal, and simultaneously, the value of phase shift determined by discrimination of the synchronizing signal is preset to a counter 6, and the CPU1 is interrupted by the end of the count to receive following data. |
