| 摘要 |
PURPOSE:To decide the level of character signal by integrating clock line signal and setting this integral value to the reference voltage for level decision. CONSTITUTION:The initial horizontal synchronizing pulse of a data input signal S1 is inputted to a monostable multivibrator cascade connected in two stages and as the output, the pulse TR (S4) which superposed on the period TCR1 in which a clock line signal is existed can be obtained. An input signal 1 (clock line signal) is gated to an integral network during only the period of pulse TR and the integral value Vm(S6) is obtained. While, the input signal is delayed by the delay circuit with TR, and it becomes S5. Picture element data signal which can not be influenced by level fluctuation and S/N ratio, by binary coding the data input signal of this S5 by setting the previously described Vm as a reference level. |
