发明名称 A CIRCUIT ARRANGEMENT IN A COIN CHECKER
摘要 <p>The coins (37) come within the coil field of an oscillator (2,6,7). Within a reverse feedback path of the oscillator amplifier (2), several resistances (11 to 18) are arranged, switchable parallel to each other individually or in any desired combination, by switching transistors (21 to 28), each controlled by a program (29). This makes the amplification controllable step by step. The program (29) has a constant-value-storage (49) with a stored standard value for the amplification in which oscillations cease whenever the field coil area is free and a calibrating resistance (35) is connected parallel to the condenser (7) of the oscillator (2,6,7). For each coin type, two pre-determined standard limit values of amplification are stored in the constant-value-storage (49), with the oscillations ceasing between them in the presence of an acceptable coin (37). Prior to each testing operation, the program (29), with calibrating resistance (35) being connected parallel to the condenser (7) increases the amplification step by step until oscillations cease. The quotient of the thus obtained amplification value and the standard value is multiplied by the two standard limit values of each type of coin, and the product is stored in the read-write-memory (59) as the nominal limit value. During the coin testing, the amplification is altered step by step from the highest nominal limit value to the next lower, and so on. A coin acceptance signal is issued whenever the oscillator oscillations do not cease with the higher of the two nominal limit values and do stop with the lower of the two nominal limit values.</p>
申请公布号 GB2090034(A) 申请公布日期 1982.06.30
申请号 GB19810035395 申请日期 1981.11.24
申请人 AUTELCA AG 发明人
分类号 G01N27/00;G07D;G07D5/08;G08B1/08;(IPC1-7):07D5/08 主分类号 G01N27/00
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