| 摘要 |
PURPOSE:To perform parallel process with the effective use of the capacity of an operator without increasing the load of the checking capacity supplied from a main storage device, by providing a high-speed data register to temporarily hold an array operand necessary for an operation plus an intermediate result of the arithmetic process. CONSTITUTION:An array operand data which is required for the operations of plural operators 10 are read out of a main storage device 1 to be stored in a data register 6 via a distributing circuit 3. At the same time, the intermediate result of the arithmetic process obtained by the operator 10 is stored in the register 6 via the circuit 3. The register 6 comprises plural high-speed registers, and the optional data given from the circuit 3 and the device 1 are distributed by the circuit 3. Then the same write address and write indication are given to the register 6 from an address control circuit 5. The data read out of the register 6 is selected by a selecting circuit 8 to be supplied to the operator 10. Thus a parallel process is carried out by the operator 10 without increasing the load of the checking capacity supplied from the device 1. |
