发明名称 CLOCK EXTRACTING CIRCUIT
摘要 <p>PURPOSE:To obtain a light-weight, small-size, and nonadjusting clock extracting circuit, by storing a maximum position detection signal of a return-to-zero single current digital code in a counter, which counts local clocks of a high frequency, to divide the frequency of local clocks. CONSTITUTION:A return-to-zero single current digital code S4 is inputted to a maximum position detecting circuit 1; and when a pulse of the code S4 becomes maximum, a detection signal S5 is transmitted to a storage terminal LD of a counting circuit 3. Local clocks S6 from a local clock generator 2 which generates clocks of an about 8-fold frequency of the clock frequency of the code S4 are inputted to the circuit 3 from a terminal CP and are counted; and when the signal S5 is applied to the circuit 3, the circuit 3 stored 1,0, and 0 from data input terminals D2, D1, and D0. That is, the phase of the circuit 3 is corrected at every maximum point of pulses of the code S4. Consequently, clocks S7 are extracted from an 8 frequency division output Q2 of the circuit 3 and are outputted.</p>
申请公布号 JPS57103450(A) 申请公布日期 1982.06.28
申请号 JP19800178512 申请日期 1980.12.17
申请人 NIPPON DENKI KK 发明人 SHIMIZU HIROSHI
分类号 H04L7/027;H04L7/02 主分类号 H04L7/027
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