发明名称 INTERRUPTION CONTROLLING SYSTEM
摘要 PURPOSE:To obtain the desired processing capacity without increasing the capacity of an interface register for the debug, etc., by realizing the decision whether or not the contents stored in the interface register shows the address of a main storage device for the interruption bit. CONSTITUTION:When an interruption bit is set, the fact that a command is stored in a command register 7 or the address storing the command within a main storage device 2 is shown to the bit. A subprocessor detects an interruption; and if the bit contents shows the former fact, the contents of the register 7 are read. Then a prescribed process is carried out based on a working program of a substorage device, and the result of this process is sent to a main processor 1. In the case of the latter fact, the subprocessor reads the command at the position of the address of a register 7 through a DMA controlling circuit 6 to carry out a prescribed process. In such way, this control method is effective for the setting of a number of command parameters in case the number of commands is numerous to be stored in the register 7 and in the case of the debug in particular.
申请公布号 JPS57103526(A) 申请公布日期 1982.06.28
申请号 JP19800179825 申请日期 1980.12.19
申请人 FUJITSU KK 发明人 YAMAMOTO NOBORU;IHI TOSHIAKI
分类号 G06F13/12;G06F9/46;G06F9/48 主分类号 G06F13/12
代理机构 代理人
主权项
地址