| 摘要 |
PURPOSE:To eliminate the need for excessive storage capacity by writing data in one of two coincident cash memories during reading operation and by writing data in the coincident cash memories during writing operation. CONSTITUTION:The high-order digit bit A1 of an address signal ADD is inputted to one-side input terminals of comparators CP1 and CP2 which correspond to a CMa and a CMb, and the low-order digit bit A2 is used to access the CMa and CMb at the same time. The readout data of the CMa and CMb obtained by the access are inputted to a selector SL1, and their addresses are inputted to the CP1 and CP2. If the CMa is hit, its hit output Hit permits a selector SL2 to switch to the side of the selector SL1 by the output of the comparator CP2. Therefore, the readout data of the hit CMa is led out through the route of the SL1 and SL2. If the CMb is hit, the readout data of the CMb is led out through the SL1 and SL2. When neither the memory CMa nor CMb is hit, data is readout of a main storage memory MM and written in the CMa or CMb which has been hit lately. |
