发明名称 BUFFER MEMORY CONTROL SYSTEM
摘要 PURPOSE:To facilitate control over a TAG2 memory for controlling buffer-memory coincidence, by making the size of an address space possessed by the TAG2 memory greater than buffer memory capacity. CONSTITUTION:An unshown storage controller reads data out of a main storage device and sends the data to a processor to retrieve the contents of a TAG2 memory 10 for the processor. The contents of the TAG2 memory 10 read by the low-order digit bits 15-23 of an address register 12 are compared 18 with the high-order digit address bits 8-14 to discriminate whether the address of the block is registered. In addition, a value obtained by decoding 13 the low-order digit bits 24 and 25 is also compared with a flag BF read out of the TAG2 memory 10. When a circuit 18 outputs a coincidence signal, an unspecific address is sent to the processor through a buffer-memory unspecifying address line 37.
申请公布号 JPS57103179(A) 申请公布日期 1982.06.26
申请号 JP19800179846 申请日期 1980.12.19
申请人 FUJITSU KK 发明人 CHIBA TAKASHI
分类号 G06F12/08 主分类号 G06F12/08
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