发明名称 INPUT/OUTPUT BUS MONITORING SYSTEM OF SEQUENCE
摘要 PURPOSE:To raise the reliability of an input/output part, by comparing an inputted external reference value with a reference value stored in an internal memory, and deciding an input bus to be abnormal, in case of dissidence as a result. CONSTITUTION:In order to monitor an abnormal state of an input/output bus 1 of a device, a reference value is set to the outside. Also, the reference value is set to a core memory in advance. Subsequently, the external reference value inputted by a sequencer is compared with the internal reference value. As a result, in case of coincidence of both of them, the input part is decided to be normal, and in case of dissidence, the input bus is decided to be abnormal. In this way, the reliability of the input/output part is raised.
申请公布号 JPS57101908(A) 申请公布日期 1982.06.24
申请号 JP19800177253 申请日期 1980.12.17
申请人 HITACHI SEISAKUSHO KK 发明人 WATANABE HIRONOBU
分类号 G05B23/02;G06F11/16 主分类号 G05B23/02
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