| 摘要 |
<p>A method and apparatus for demodulating a received differentially encoded phase modulated carrier signal in which the carrier signal is phase shifted during each modulation period of the carrier to represent one of four pairs of binary bits or dibits. A first clock generates first clock pulses (RDCL) in response to the detection of the start of each data interval in the received carrier signal, and a second clock provides second clock pulses (77) adjusted to the phase of the first clock pulses. The second clock pulses are used to synchronize the demodulator in establishing the location of the modulation period of the incoming carrier. In order to overcome errors found in the decoding of the carrier signal, the adjustment of the phase of the second clock is suppressed when the dibits 00 and 10 are being decoded. With this construction, it was found that the second clock may run out of synchronization if long strings of 00 or 10 dibits are received. In order to solve this problem, after a predetermined number of continuous 10 or 00 dibits have been decoded, the suppression of the adjustment of the phase of the second clock is disabled.</p> |
