| 摘要 |
PURPOSE:To shorten the necessary time of a test of reliability by reading all memory cells, connected to a selected row line, simultaneously, by applying a prescribed potential of column lines of a memory cell array when a reliability test signal is inputted. CONSTITUTION:For a test of reliability, when an input terminal -CE is held at a prescribed level higher than 10V, a test control circuit 19 generates a ''1''- level output and transistors (TR) 18 for test potential supply control all turn on to apply a constant potential to all column lines 12. Further, a ''0'' level signal from the output terminal of a memory periphery control circuit 20 is supplied to peripheral circuits, and memory chips are put in operation. Therefore, currents flow through all memory cells connected to one row line selected by a row decoder 13, and the occurrence of fault of the cells is discriminated by the output of a buffer 17. Thus, memory test time is shortened. |
