| 摘要 |
PURPOSE:To receive a sent-back signal correctly by obtaining judgement criteria H and L by adding an odd parity bit to the sent-back signal from a terminal equipment and counting its pulse width by using a reference clock at a master equipment. CONSTITUTION:When a sent-back signal is received from a terminal equipment, a gate 2 permits a counter 1 to count a reference clock, and at the trailing edge of the sent-back signal, an interruption signal INT is inputted to a CPU4 through an FF5. The CPU4 sets an input port 3 in a read state by its chip selection signal CS to read the value of the counter 1, and also resets the FF5 to invert its Q output to a level L. This operation is repeated as many times as the number of sent-back signal pulses to collect data, and the CPU adds an odd parity bit to the sent-back pules; and the width of the sent-back pulse is calculated by using the count value to find maximum pulse width Fmax, and a sent-back signal sequence is reproduced on the basis of levels H and L three fourth the Fmax as judgement criteria. Consequently, correct reception is performed even if the terminal has frequency variation and temperature variation. |
