| 摘要 |
PURPOSE:To reduce the signal transmission line for numeral display, by transmitting pulses with pulse frequency modulation sequentially with a plurality of binary coded decimal (BCD) codes. CONSTITUTION:A clock pulse oscillator 21 generates a clock pulse (cp) in frequency f1 and inputs it to a selection circuit 24 and a frequency dividing counter 22. The frequency division counter 22 generates frequency dividing pulses DS1, DS2, DS3 of different frequency. A binary signal set at a numeral setter 1 is inputted to a shift register 23 in parallel and read out with the frequency dividing pulse DS2 and inputted to a sequential selection circuit 24. The selection circuit 24 selects either one of the clock pulse (cp) and the frequency dividing pulse DS1 with a signal from the shift register 23 and inputs it to an AND circuit 27. NOT signal of other pulses DS2, DS3 is inputted to an AND circuit 27 and the output is sequentially transmitted to the reception side through an output circuit 28. |
