| 摘要 |
PURPOSE:To enable decoding in high speed, by decoding only throygh retrieval of the decoding table once per signal one bit. CONSTITUTION:A memory 3 storing a modified Haffmann code (MH code) decoding table is accessed with a signal (d) outputted from an address generating circuit 1, signal (c) outputted from a reception data storage circuit 2 and signal (e) outputted from a black-and white signal generating circuit 6 to output the signals (f)-(h). When the signal (f) is at H level and the signal h is at L level, a gate 9 outputs a latch instruction signal i to a run length latch circuit 4. When the signals (f) and (h) are both at H level, a gate 10 outputs a latch instruction signal h' to a run length latch circuit 5. A facsimile signal generating circuit 7 outputs write-in clock (m) the same number as the run length loaded in a line memory 8 and resets the run length latch circuits 4, 5. The line memory circuit 8 forms a facsimile signal and stores it with a white-and-black signal (e) and the write-in clock (m). |
