| 摘要 |
PURPOSE:To decrease the occupied area at circuit integration on a wafer, through a common use of power supply lines, by constituting logical product terms with a series connection of enhancement and depletion MOS-FETs. CONSTITUTION:When input signals 21, 24 are at ''0'', E-FETs 2, 4 are turned off and an output line 27 is at ''1''. On other output lines 28-30, at least one of E-FETs 8, 9, 12, 15, 18, 20 of the system turns on, and since D-FETs 7, 10, 13, 14, 17, 19 are turned on at all times, the output is at ''0''. Similarly, when the input signal 21 is at ''0'' and the signal 24 is at ''1'', the output line 29 only is at ''1'', and when the input signals 21, 24 are at ''1'', the output line 30 only is at ''1''. |
