发明名称 PROCESSING SYSTEM FOR MEMORY ACCESS FAULT
摘要 PURPOSE:To prevent a memory access fault from being latent, and to prevent it from becoming a permanent fault, by requesting an interruption by means of reexecution of hardware, to a fault which is not permanent, and monitoring and recording it by software. CONSTITUTION:When a CPU4 is reading out a data to a memory 1, its data is inputted to a parity error detecting circuit 48, and when an error is detected, a reexecution request signal RT is inputted to a controlling circuit 40. As a result, the circuit 40 discriminates occurrence of the error, finishes the read-out operation, and designates the same address without intervention of software, by which reexecution as hardware is performed. In this way, in case when the reexecution is normal, a low level interruption request signal LI is inputted to the circuit 40, and address information related to said fault, and the number of times of occurrence of the interruption request are recorded by the prescribed software processing.
申请公布号 JPS5798200(A) 申请公布日期 1982.06.18
申请号 JP19800174590 申请日期 1980.12.12
申请人 HITACHI SEISAKUSHO KK 发明人 IWAKI SHINICHI;OONUMA TATSUMASA
分类号 G06F12/16;G06F11/00;G06F11/14 主分类号 G06F12/16
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