发明名称 |
INTEGRATED CIRCUIT CHIP CAPABLE OF INSPECTING BURIED MEMORY ARRAY |
摘要 |
An integrated circuit chip having an embedded array which is not directly accessible from the primary input/output chip pins is manufactured with additional test circuitry directly on the chip, such that the performance of the array may be physically tested from the input/output pins by an external chip tester while the array remains embedded. Because of the added test circuitry, tests are not limited to the original chip architecture, and a variety of array tests may be made by an external tester without redesigning the chip architecture. |
申请公布号 |
JPS5797641(A) |
申请公布日期 |
1982.06.17 |
申请号 |
JP19810137882 |
申请日期 |
1981.09.03 |
申请人 |
INTERN BUSINESS MACHINES CORP |
发明人 |
DAGURASU DABURIYUU UESUTOKOTSUTO |
分类号 |
G11C29/00;G01R31/28;G01R31/3185;G11C29/02;G11C29/20;G11C29/56;H01L21/66;H01L21/822;H01L27/04 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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