发明名称 INSTRUCTION PROCESSING SYSTEM
摘要 PURPOSE:To shorten a shifting time from generation of an error to start of restart execution, by a simple configuration, by accessing a control memory in accordance with a result of parity check of plural local memories, and reading out and controlling the corresponding control program. CONSTITUTION:This system is provided with a control memory 4, plural local memories 2 storing the same data, respectively, and the respective parity checking circuits 9, and in accordance with whether a read-out data of each memory 2 is correct or not, an available pattern of all the memories 2 is changed and the instruction is reexecuted. In this case, an address corresponding to the memory 4 is inputted to a register 4, also a controlling program corresponding to an availabe pattern of the memory 2 is stored in the memory 4 in advance so that an address to be set to the register 4 is controlled in accordance with an output of the circuit 9, the control memory 4 is accessed in accordance with a check result of the circuit 9, a corresponding control program is read out, by which the control is executed.
申请公布号 JPS5797150(A) 申请公布日期 1982.06.16
申请号 JP19800173459 申请日期 1980.12.09
申请人 FUJITSU KK 发明人 SHIRANAGA MATSUO
分类号 G06F12/16;G06F11/14 主分类号 G06F12/16
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