| 摘要 |
PURPOSE:To raise the processing efficiency, by detecting a working state of prescribed timing, and idle timing, and starting the next access from the idle timing. CONSTITUTION:A processing instruction is inputted to a decoder 20, and the instruction converted to a code is inputted to an insturction start controlling circuit 21. The instruction start controlling circuit 21 detects an idle timing by an idle detecting circuit 22 of a bank timing in accordance with the inputted instruction, and also detects a working state of the first ooerand by a detecting circuit 23. Moreover, the instruction is inputted to a multiplying instruction and adding instruction processing and controlling circuit 24 and 27, respectively, the timing of the banks which said circuits are using is controlled by controlling circuits 25, 28, the residual cycle number of said mutiplication and addition is controlled by controlling circuits 26, 29, and it is informed to the instruction start controlling circuit 21 that said residual cycle number is <=10. The instruction start controlling circuit 21 gives a command to start the instruction, to a vector register, by the idle detecting signal of the bank timing in its own circuit, and a signal informing that the residual cycle number is <=10. |
