| 摘要 |
PURPOSE:To efficiently execute a buffer nullification control, by providing (n) pieces of buffer nullification address detecting means and (n-1) pieces of comparing circuits for comparing a store address, and forcibly outputting the dissidence by the (i+1)-th buffer nullification address detection means. CONSTITUTION:A store address A from a vector unit is set to a tag access register 11, a tag part 15 is read-accessed by a lower bit, a read-out data is set to a read-out data register 23, and an upper bit of the store address A is set to a comparing address register 19. A comparing circuit 27 compares the contents of the comparing address register 19 with those of the tag read-out data register 23, and when both have coincided, the coincidence is outputted. A comparing circuit 31 compares a line address part of the store address A with a line address part of a store address B, and when the comparing circuit 31 outputs the coincidence, an output of a comparing circuit 28 is forced to dissidence. |
