| 摘要 |
PURPOSE:To obtain output having gate dielectric resistance or lower when drain voltage is high by projecting a high resistance surface layer having the same conduction type as a drain extending from a drain of a SOS-IGFET from an offset gate side surface section and forming an intermediate terminal. CONSTITUTION:A P type Si substrate layer 2 is shaped onto an insulating substrate 1 made of sapphire, etc., an N<+> type source 3 and the drain 4 are formed, and an offset gate electrode 6 is shaped on the surface between the source and the drain through a gate insulating film 9. The N type high resistance surface layer 5 is extended in the source 3 direction from the drain 4. The P type substrate layer 2 and the N type surface layer 5 are stretched on the insulating substrate 1 in projecting shapes from one part of the side surface of an offset gate region, connected to a high impurity concentration N type region 10 and coupled with an intermediate terminal electrode 11. Accordingly, the output voltage of gate dielectric resistance or lower of the next stage FET can be taken out of the intermediate terminal while increasing drain dielectric resistance, and the high-voltage circuit can be formed. |
