| 摘要 |
PURPOSE:To achieve speed up of IC operation by a method wherein a dimension of output transistor element in a unit gate circuit constituting a logic circuit is charged and the delay time of the unit gate circuit is maintained constant. CONSTITUTION:A FET constituting a NOR gate and a diode help form the NOR gate as desired so that an n epitaxial layer on semiinsulated GaAs substrate is formed as an active layer, the n epitaxial layer is removed partially so as to leave selectively only a region forming the FET and Schottky diode and consequently an island is formed, the Schottky diode and the FET are provided in the island and a wiring for the FET and Schottky diode is established by insulating the interlayer with SiO2. At this time, by changing the crosssection of the path of the equivalent current which increases the gate width of output FETT4 in response to a fan-out number, the delay time of the NOR gate unit can be maintained constant regardless of the fan-out number, consequently an optimum high speed logic IC can also be formed. |
