| 摘要 |
PURPOSE:To determine the phase of discrimination timing properly to obtain the superior equalization capability of wide-range discrimination timing, by constituting a delay circuit with taps of an automatic equalizer by combinations of taps having a prescribed delay time difference for the repeating period of an input signal. CONSTITUTION:A delay circuit 22 with output taps 23-29 which delay an input signal is provided in an automatic equalize, and the input signal is weighten in accordance with tap outputs of the circuit 22 by weighting circuits 210-216, and the total sum of outputs of circuits 210-216 is operated by an adder 217. The output of the adder 217 is discriminated in multiple levels by a discriminator 218, and correlation quantities between the discrimination error and respective tap outputs of the circuit 22 are obtained by correlators 219-225 to generate control voltages of circuits 210-216. The delay time difference between respective adjacent taps of taps 23-25 and taps 27-29 of the circuit 22 is set to a value equal to an input pulse repeating period T, and the delay time difference between respective adjacent taps of intermediate taps 25-27 is set to a value equal to T/2, thus determining a phase of a wide-range discrimination timing. |
