| 摘要 |
PURPOSE:To make a logical amplitude conversion of a good response characteristic possible with a low power consumption, by using plural IG FETs to constitute a positive feedback loop and by controlling them by an input signal and a signal obtained by inverting the polarity of the input signal. CONSTITUTION:A voltage Vin applied to an input terminal 11 is inputted to the gate of an N type IG FET16 and an inverter IV13 to which a voltage VDD1 is supplied, and the voltage Vin is inverted by the IV13 and is inputted to an N type IG FET17. Drains of FETs16 and 17 are connected to drains of P type FETs 14 and 15 to which a voltage VDD2(>VDD1) is supplied, output terminals 18 and 20, and gates of FETs 15 and 14. When the level of the input signal is low, FETs 15 and 16 are turned off, and FETs 14 and 17 are turned on, and the terminal 18 is high-level, and the terminal 20 is low-level. When the input signal changes from the low level to the high level, FETs 15 and 16 are turned on, and FETs 14 and 17 are turned off, and the terminal 18 becomes low- level, and the terminal 20 becomes high-level. Since the power is consumed only for a very short time of switching of FETs 14 and 15, the power consumption is very small. |
