| 摘要 |
PURPOSE:To greatly reduce the quantity of hardware, by eliminating a double structure of an arithmetic circuit. CONSTITUTION:An arithmetic circuit 1 calculates a function F(X) and a function GY in cycles T1 and T2, respectively. An arithmetic circuit 2 calculates the function GY and the function F(X) in cycles T1 and T2, respectively. A switching circuit 31 switches and delivers a variables (x) and (y) to the circuit 1 in cycles T1 and T2, respectively. A switching circuit 32 switches and delivers variables (y) and (x) to the circuit 2 in cycles T1 and T2, respectively. Furthermore, a comparator 51 compares the output of an arithmetic result register 3 with the output of the circuit 2; and a comparator 52 compares the output of an arithmetic result register 4 with the output of the circuit 1. In case no coincidence is obtained through the comparison carried out at the comparators 51 and 52, a dissidence signal is produced from a dissidence signal generator 6 to inform the operator of an error of operation. |
