发明名称 ARITHMETIC DEVICE
摘要 PURPOSE:To simplify the diagnosing procedur of hardware with high efficiency, by securing an optional operation fo the parity bit. CONSTITUTION:An operated including a parity bit P is set to an input register 1, and an operand of one byte is set to an input register 2 of the other side. These outputs receive an arithmetic operation by a selection circuit 5, an arithmetic circuit 7, a selection circuit 13, a parity producing circuit 6, an output register 4, a selection circuit 15, etc. During the diagnosis of hardware, etc., the data bit in the reigster 1 is directly set to an output register 4 in the form of an output data bit. For the parity bit, however, the result obtained through a logical arithmetic carried with the specific bit of the contents of the register 2 is set to the register 4 in the form of an output parity bit. Accordingly, the output parity bit can be freely operated by the data which is applied to the register 2.
申请公布号 JPS5794842(A) 申请公布日期 1982.06.12
申请号 JP19800171010 申请日期 1980.12.05
申请人 HITACHI SEISAKUSHO KK 发明人 OGAWA TETSUJI
分类号 G06F11/10;G06F7/38;G06F11/267 主分类号 G06F11/10
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