发明名称 CLOCK SYNCHRONIZING CIRCUIT
摘要 <p>PURPOSE:To simplify the circuit, by resetting an N-frequency-division counter for synchronism, with a clock picked up at the clock synchronizing pattern reception through the use of carrier set to N times the clock frequency. CONSTITUTION:A 2-phase PSK modulation wave inputted to a terminal 101 is phase-detected with an output of a voltage controlled oscillation circuit 12 at a phase detection circuit 11. In this case, the output of an inversion circuit 15 and that of the circuit 12 are phase-compared at a phase comparison circuit 14, and the phase of the circuit 12 is controlled by the output. Further, the output of the circuit 11 is differentiated at a differentiation circuit 16 to pick up a clock component and counted at an integration circuit 17. When the count value is a specified number or more in a specified period, a reset signal is transmitted to an N-frequency-division counter 14. Thus, the counter 14 which performs N-frequency-division of the output of the voltage controlled oscillation circuit 12, i.e., reproduced carrier, can be synchronized with the phase detection data of the output of the phase detection circuit 11.</p>
申请公布号 JPS5793748(A) 申请公布日期 1982.06.10
申请号 JP19800170061 申请日期 1980.12.02
申请人 NIPPON DENKI KK 发明人 EGUCHI IWAO
分类号 H04L7/00;H04L7/033;H04L27/22 主分类号 H04L7/00
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