| 摘要 |
<p>PURPOSE:To eliminate erroneous erasure by separating the writing and erasure part of a transistor (TR) for storage from a main body, by making its source floating, and by arranging a floating wiring in parallel to a column line. CONSTITUTION:Storing and selecting MOS transistors (TR) are divided into an MOSTRQ11 and a writing and erasure part Q12, and TRs Q21 and Q22 for selection. Further, control gate CG wiring is made parallel to a column line Y. For writing operation, the Y and X of a selected cell are held high in level and the Y' is held at level zero to turn on the TRs Q21 and Q22, and a high voltage is applied to the drain of the TRQ11 and its writing and erasure diffused area WED. Since the gate CG is held at the level zero, electrons are extracted from the floating gate FG of the TRQ12 to the area WED, thus performing the writing operation. In a half-selected or unselected cell, the high voltage is not applied to the drains of the TRs Q11 and Q12, so the writing operation is not performed. To erase all data at a time, the Y, and X and Y' of every cell are held at the level zero and high level, electrons are applied from the FG of the TRQ12 to the WED, thereby performing the erasure.</p> |
