| 摘要 |
PURPOSE:To set the output timing of a timing pulse freely with simple constitution by using an optional bit output of a shift register, controlled by a flip- flop, etc., as the timing pulse. CONSTITUTION:An access signal from a gate 12 sets an RS type FF14 and the the output Q of the FF14 is synchronized with a clock signal by a D type FF16 through an AND gate 15 to input the output Q of the FF16 to a shift register 17 in series. Consequently, the output of the shift register 17 is shifted, bit by bit, successively to bits 1, 2.... With the desired two-bit output of this shift output, the output timing of a multiplexer 20 and a gate 21 which generate an address signal and a column address strobe signal respectively is controlled to attain access, etc., to a dynamic RAM11. Selecting the desired bit output of this shift register setting of the output timing of a timing pulse is performed freely with simple constitution. |
