Binary balancing apparatus for semiconductor transducer structures

摘要

There is disclosed a balancing network for a piezoresistive semiconductor bridge configuration. The balancing network comprises a plurality of series resistors arranged in series with the sensing elements in the bridge configuration. Each resistor differs from the previous one according to a power of two to form a binary ladder arrangement. The individual resistors are associated with terminals to allow the transducer manufacturer to selectively short one or more resistors to provide zero balance compensation. The resistors are located on the nonactive portion of the semiconductor substrate and are fabricated by the same techniques employed for fabrication of the semiconductor piezoresistive sensing elements to assure temperature tracking of the unit with the desired temperature operating range.