Error correcting code system

摘要

An error correcting code mechanism for SEC-DED (16, 21) or (8, 12) code to correct data bit errors caused by alpha particle impingement into high density storage units. The data word is read into and out of a high density storage unit and generated check bits are stored in low density storage immune to alpha particle radiation. Data bits and check bits, addressed in parallel are read out to error detecting and correcting circuits to determine the existence of an error only in a data bit and correct the state of the erroneous bit. The number of check bits and required parity and checking circuitry is reduced since no error checking of check bits, presumed to always be correct because of the use of low density storage occurs.