发明名称 BUS CONTROLLING SYSTEM
摘要 PURPOSE:To reduce the transfer time of data, by controlling a switch provided to a bus line which is connected in common to plural logic blocks and then ensuring the use of the bus line after dividing it in terms of the space. CONSTITUTION:Switches 11 and 12 are provided to a bus line 101 which is connected in common to plural logic blocks 1-5. Then the line 101 is divided in terms of the space by controlling the switches 11 and 12. Thus the line 101 can be used. For instance, the the switches 11 and 12 are inserted to the line 101 as shown in the diagram, and a switch controller 10 is provided to control ON/ OFF of these switches. Control lines 201 and 202 are connected to the switches 11 and 12 through the controller 10. The switches 11 and 12 are controlled by the controller 10 by turning on and off based on the prescribed sequence or in accordance with the state of the system at that moment (such as a program control) and other methods.
申请公布号 JPS5790733(A) 申请公布日期 1982.06.05
申请号 JP19800166547 申请日期 1980.11.28
申请人 HITACHI SEISAKUSHO KK 发明人 KOYAMA TOSHIAKI
分类号 G06F13/36;G06F3/00;G06F13/40 主分类号 G06F13/36
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