Decoding circuit for coded mark inversion - has entirely digital circuits for production of clock signals which are each given preset delays

摘要

The decoder for 'Coded Mark Inversion' signals includes four sub-assemblies, two of which are conventional. The third sub-assembly is a digital circuit elaborating the intermediate signal. It includes an inverter to receive the signal and provide the inverse signal which is then delayed by an interval delay circuit. The resulting signal is identified. Another delay circuit also receives the signal and delays it by a time ,T, to provide a signal. The identified and delayed signals are applied to a logic OR-circuit, which provides a signal. This is subsequently delayed by T/4 by a circuit (62) to provide the signal, I. The fourth sub-assembly is a circuit which is entirely digital to elaborate the clock signal, H.