发明名称 LINE CONTROL SYSTEM
摘要 PURPOSE:To prevent the overrun and the underrun of data, by providing a transmission first in first out (FIFO) quenue controlled to fill with data and a receiving FIFO queue controlled to be empty of data. CONSTITUTION:Data is transferred between a transmission FIFO queue 240 and a receiving FIFO queue 250 and a data transmitting and receiving circuit 220 synchronously with timing signals ST' and RT' generated by a timging generating circuit. The transmission FIFO queue has a function which detects whether it is filled up with transmission queuing data or not, and the detection signal is applied to the timing generating circuit to stop the generation of the timing signal ST'. The receiving FIFO queue has a function which detects whether stored contents are zero or not, and the detection signal is applied to the timing generating circuit to stop the generation of the timing signal RT'.
申请公布号 JPS5789358(A) 申请公布日期 1982.06.03
申请号 JP19800164846 申请日期 1980.11.22
申请人 NIPPON DENSHIN DENWA KOSHA;FUJITSU KK 发明人 YASHIRO ZENICHI;NISHIWAKI MINEO;ARIMA SHIYUUHEI
分类号 H04L29/02;G06F5/06;G06F13/00;H04L13/08 主分类号 H04L29/02
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