| 摘要 |
PURPOSE:To access an element, by prescribing a timing for accessing an element of a vector register of each bank, providing a controlling circuit for controlling whether the prescribed timing is used or not, and selecting the prescribed timing. CONSTITUTION:From the center of the first and second bits and the center of the fourth and fifth bits of a shift register 20, the respective outputs are inputted to an addition register 20, the respective outputs are inputted to an addition processing circuit 22 and a multiplication processing circuit 23. On the other hand, an output of a decoder 21 which has received an instruction as an input is also inputted to the circuit 22 and 23. Also, outputs of use displaying circuit 26, 27 of timings ABC, DEF are inputted to the circuits 22, 23, respectively. For instance, the addition processing circuit 22 detects that the ABC timing is being used and the DEG timing is unused, and if the next instruction inputted to the decoder 21 is an adding instruction, its adding instruction is received by the addition processing circuit 22, and the addition processing is started by the DEF timing. |
