| 摘要 |
PURPOSE:To easily perform testings on a package loaded on the titled circuit by installing a means which forms a shift register which connects plural FF circuits in tandem in response to shift designation inputs, and freely reading or setting input side data and output side data. CONSTITUTION:Normal input terminals 5-1-5-N and normal output terminals 8-1-8-L are installed to the main body of an integrated logical operation circuit 1. Input side FFs 4-1-4-N and output side FFs 7-1-7-L are respectively connected to each terminal 5-1-5-N and 8-1-8-L, and, when a test designation input is given to a test mode control terminal 10, the FFs 4-1-4-N and 7-1-7-L are slowly advanced in synchronizing to the clock of a clock signal input terminal 11. When no designation input is given to the terminal 10, the input signal is passed under the same condition. Moreover, in response to a designation input from a shift mode control terminal 9, FFs 4-1-4-N and 7-1-7-L are connected in tandem, and they operate as a shift register to make the test of an internal circuit 2 easier. |
