| 摘要 |
<p>A clock generator circuit for generating two pairs of clock signals (φ2, φ2 - φ1, φ1) comprises a NAND circuit (51) and a NOR circuit (52) cross-coupled to each other and each having an input for receiving a reference clock signal (φ0). A first inverter (53) is provided between the output of the NAND cicuit (51) and the other input of the NOR circuit (52), and a second inverter (54) is provided between the output of the NOR circuit (52) and the other input of the NAND circuit (51). A pair of clock signals (φ2, φ2) are generated from the NAND circuit (51) and the first inverter (53), while the other pair of clock signals (φ1, φ1) are generated from the NOR circuit (52) and the second inverter (54). Unwanted overlap of such clock signals can thereby be avoided.</p> |
