| 摘要 |
A non-volatile semiconductor latch having at least one variable threshold FATMOS transistor in the cross-coupled latch branches. To accomplish non-volatile reading, the latch nodes (X1, X2) are briefly precharged positively so that when the precharging ends and the nodes descend towards the negative supply voltage, the FATMOS(s), by virtue of their varied thresholds, place the latch in its correct logic state dictated by an earlier non-volatile write operation. Precharging, by means of transistors Q7, Q8 in parallel with the complementary drivers or loads, and transistors Q9, Q10 in series with the drivers in the latch, negates the capacitive effects which can otherwise cause unpredictable non-volatile reading. It also enables non-volatile reading to occur independently from power switch-on-which was necessary with earlier non-volatile FATMOS-containing latches.
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