发明名称 COMPENSATING SYSTEM FOR STEP OUT OF PCM SIGNAL
摘要 PURPOSE:To keep intervals of synchronizing signals in a data signal normal, by increasing or decreasing the number of clocks by the number of bits for the step-out of data at the time of the least data loss in case that the step-out of synchronization is detected during reproducing of a PCM signal. CONSTITUTION:Synchronizing signals are detected from a disc reproduced signal, and the irregularity of intervals of detected synchronizing signals is detected, and data is written to a storage element 21 by a clock signal phi1' where the number of clocks is increased or decreased by the number of bits for the step- out of data at the time of the least data loss on a basis of the detection signal, and data is read out by a clock signal phi2, which is not subjected to this adjustment for the number of clocks, to compensate the step-out of synchronization. Thus, intervals of synchronizing signals in the data signal are kept in a normal state.
申请公布号 JPS5787252(A) 申请公布日期 1982.05.31
申请号 JP19800162366 申请日期 1980.11.18
申请人 ZENERARU:KK 发明人 SHINOHARA TATSUKOSHI
分类号 H04J3/06;H04L7/00;H04L7/08 主分类号 H04J3/06
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