| 摘要 |
<p>PURPOSE:To reduce the repeating delay and reduce the cost, by inhibiting the input by an abort sequence and by inputting a pseudo flag sequence by a flag sequence, in the data repeater which repeats a bit synchronizing signal. CONSTITUTION:A data repeating installation 4' takes receiving data into a bit buffer 48 as serial data still synchronously with the synchronizing signal extracted from data received from a terminal equipment 3 and outputs data in the bit buffer 48 in serial synchronously with the synchronizing signal of an MODEM. If the frequency of the synchronizing signal extracted from receiving data is higher than that of the synchronizing signal of the MODEM, the input of the bit buffer 48 is inhibited temporarily when an abort sequence is issued from the terminal equipment 3. When the number of bits of data stored in the bit buffer 48 is decreased to a prescribed number, the data input is restarted. If the frequency of the synchronizing signal extracted from receiving data is lower than that of the synchronizing signal of the MODEM, a pseudo flag sequence is inputted to the bit buffer 48 just after a flat sequence is transmitted from the terminal equipment 3, thus absorbing the frequency shift.</p> |
