| 摘要 |
PURPOSE:To fix the phase of an output frequency to an external clock, by performing the frequency conversion including pulse interleaving processing for the output of a transmitter, in a PLL circuit and synchronizing the removal of pulse of an operation circuit fed back to the phase comparasion to an external clock. CONSTITUTION:Clocks in 2048kHz and 8kHz are present in the station of a PCM24 to form 1.554MHz used for PCM. A clock input S1 in 2048kHz is frequency-divided to 1/4 at a frequency divider 10 and inputted to a phase comparator PC. On the other hand, the input is inputted to a 1544kHz 193-notation counter 22 of an output S2 of a VCO16 to produce a carry S3 every 193 counts, an inhibition gate 24 is actuated and clock pulse to a ternary counter 18 is blocked for inerleave operation, and the output of the counter 18 is a frequency of 512kHz. The counter 22 is cleared with the carry S3 or the clock S4 of external 8kHz and synchronized, and the frequency divider 10 is synchronized at the same time. The output of the phase comparator PC is supplied to the VCO 16 via an LPF14 to control the frequency of oscillated clock. |
