| 摘要 |
PURPOSE:To increase the working frequency, by successively delaying the clocks the delay due to the wiring and then distributing then to each of the FFs in accordance with the sequence of the signal flow. CONSTITUTION:A clock (clk) is supplied to a clock terminal C of a flip-flop FF1 through a binary sequence circuit and then to the terminal C of the next FF2 from the first terminal C via a wiring (a). Furthermore this clock is supplied to the terminal C of an FF3 via a wiring (b). A delay time such as several ns is caused through the wirings (a) and (b), and the input signal is transmitted in a sequence of FF1-FF3. Thus the input signal is delayed by the FF1-FF3 plus OR circuits G1 and G2, and at the same time the clock (clk) is also delayed through the wirings (a) and (b). As a result, for instance, the delay time between the inputs of FF1 and FF2 is equivalent to the value which is obtained by subtracting the delay time of the clock (clk) caused by the wiring (a) from the sum of the wiring delay time of the FF1 and the circuit G1. |
