发明名称 VARIABLE DELAY CIRCUIT
摘要 PURPOSE:To vary only the extent of delay continuously while realizing flat delay characteristics, by varying the center frequencies and/or Q values of two variable delay equalizers connected in series. CONSTITUTION:Two constant-impedance BPF type variable delay equalizers 1 are 2 are connected in series, and center frequencies fa and fb, and Qa and Qb of those variable delay equalizers 1 and 2 are varied by a control circuit 3. Some constant Q characteristics are shown by solid lines, and the control circuit 3 varies the Qs of the variable delay equalizers 1 and 2 to vary the extents of delay as shown by dotted lines. In the graph, (a) is the center frequency fa and (b) is variable delay characteristics of the center frequency fb; and (a+b) in an in-use range A is as shown by (c) and the composite extent of delay is as shown by the dotted lines, making the composite extent of delay variable. Even when the center frequencies fa and fb are varied, the composite extent of delay varies similarly.
申请公布号 JPS5783915(A) 申请公布日期 1982.05.26
申请号 JP19800159833 申请日期 1980.11.13
申请人 FUJITSU KK 发明人 ITAYA EIJI
分类号 H03H7/30;H03H7/01;H04B3/14 主分类号 H03H7/30
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