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经营范围
发明名称
摘要
PURPOSE:To digitize the PLL (phase locked loop) circuit in order to realize an adjustment-free operation, small size, high reliability and low cost.
申请公布号
JPS5724700(B2)
申请公布日期
1982.05.25
申请号
JP19760139265
申请日期
1976.11.19
申请人
发明人
分类号
G11B20/14;H03L7/00;H03L7/06;H04L7/033
主分类号
G11B20/14
代理机构
代理人
主权项
地址
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