发明名称 FAULT PROCESSING CIRCUIT
摘要 PURPOSE:To easily specify a faulty part, by adding an inhibiting circuit, and inhibiting fault information through a combining circuit from a fault generation source. CONSTITUTION:A fault detected by a fault detecting circuit 14 in accordance with an output data from a combining circuit 4 is fatched by a signal 64, and is inputted to a 3-input AND43 and a 2-input AND44 of an inhibiting circuit part5. To the other input terminal of the 3-input AND43, output signals 61, 62 of fault detecting circuits 11, 12 of registers 1, 2 are inputted through inverters 41, 42, and set a fault information holding part 24 by taking OR with an AND output of a flip-flop 40 which becomes ''1'' at the time of testing whether the detecting circuit 14 is normal or not. According to this operation, a data containing a fault is not set to a fault holding circuit part corresponding to the combining circuit in accordance with a register in which the fault has occurred, therefore, the faulty part is specified easiy.
申请公布号 JPS5781653(A) 申请公布日期 1982.05.21
申请号 JP19800158003 申请日期 1980.11.10
申请人 NIPPON DENKI KK 发明人 KITAMURA NOBUAKI
分类号 G06F11/34;G06F11/00;(IPC1-7):06F11/00 主分类号 G06F11/34
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